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M36L0R8060T0 M36L0R8060B0 256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package PRELIMINARY DATA FEATURES SUMMARY MULTI-CHIP PACKAGE - 1 die of 256 Mbit (16Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory - 1 die of 64 Mbit (4Mb x16) Pseudo SRAM SUPPLY VOLTAGE - VDDF = VCCP = VDDQ = 1.7 to 1.95V - VPP = 9V for fast program ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code M36L0R8060T0: 880Dh - Bottom Device Code M36L0R8060B0: 880Eh PACKAGE - Compliant with Lead-Free Soldering Processes - Lead-Free Versions FLASH MEMORY SYNCHRONOUS / ASYNCHRONOUS READ - Synchronous Burst Read mode: 54MHz - Asynchronous Page Read mode - Random Access: 85ns SYNCHRONOUS BURST READ SUSPEND PROGRAMMING TIME - 10s typical Word program time using Buffer Enhanced Factory Program command MEMORY ORGANIZATION - Multiple Bank Memory Array: 16 Mbit Banks - Parameter Blocks (Top or Bottom location) DUAL OPERATIONS - program/erase in one Bank while read in others - No delay between read and write operations SECURITY - 64 bit unique device number - 2112 bit user programmable OTP Cells Figure 1. Package FBGA TFBGA88 (ZAQ) 8 x 10mm BLOCK LOCKING - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WPF for Block Lock-Down - Absolute Write Protection with VPPF = VSS COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK PSRAM ACCESS TIME: 70ns ASYNCHRONOUS PAGE READ - Page Size: 16 words - Subsequent read within page: 20ns LOW POWER FEATURES - Temperature Compensated Refresh (TCR) - Partial Array Refresh (PAR) - Deep Power-Down (DPD) Mode SYNCHRONOUS BURST READ/WRITE December 2004 1/18 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M36L0R8060T0, M36L0R8060B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Chip Enable input (EP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/18 M36L0R8060T0, M36L0R8060B0 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Figure 5. Figure 6. Table 5. Table 6. Table 7. Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. TFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15 Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3/18 M36L0R8060T0, M36L0R8060B0 SUMMARY DESCRIPTION The M36L0R8060T0 and M36L0R8060B0 combine two memory devices in a Multi-Chip Package: a 256-Mbit, Multiple Bank Flash memory, the M30L0R8000T0 or M30L0R8000B0, and a 64Mbit PseudoSRAM, the M69KR096A. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to `1'). Figure 2. Logic Diagram VDDQ VPPF VCCP 16 DQ0-DQ15 EF GF WF RPF WPF L K EP GP WP CRP UBP LBP M36L0R8060T0 M36L0R8060B0 WAIT EF GF WF RPF WPF Chip Enable input Output Enable Input Write Enable input Reset input Write Protect input Table 1. Signal Names A0-A23 DQ0-DQ15 L K WAIT VDDF VDDQ VPPF VSS VCCP NC DU Address Inputs Common Data Input/Output Latch Enable input for Flash memory and PSRAM Burst Clock for Flash memory and PSRAM Wait Data in Burst Mode for Flash memory and PSRAM Flash Memory Power Supply Common Flash and PSRAM Power Supply for I/O Buffers Flash Optional Supply Voltage for Fast Program & Erase Ground PSRAM Power Supply Not Connected Internally Do Not Use as Internally Connected VDDF 24 A0-A23 Flash Memory Signals PSRAM Signals EP GP WP CRP UBP LBP Chip Enable Input Output Enable Input Write Enable Input Configuration Register Enable Input Upper Byte Enable Input Lower Byte Enable Input VSS AI09312 4/18 M36L0R8060T0, M36L0R8060B0 Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 6 7 8 A DU DU DU DU B A4 A18 A19 VSS VDDF NC A21 A11 C A5 LBP A23 VSS NC K A22 A12 D A3 A17 NC VPPF WP EP A9 A13 E A2 A7 NC WPF L A20 A10 A15 F A1 A6 UBP RPF WF A8 A14 A16 G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT NC H GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J NC GF DQ9 DQ11 DQ4 DQ6 DQ15 VDDQ K EF DU DU NC VCCP NC VDDQ CRP L VSS VSS VDDQ VDDF VSS VSS VSS VSS M DU DU DU DU AI09313 5/18 M36L0R8060T0, M36L0R8060B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A23). Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The other lines (A23-A22) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory internal state machine or they select the cells to access in the PSRAM. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable signal (EP) and the Write Enable signal (WP). Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance. Latch Enable (L). The Latch Enable pin is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KR096A for the PSRAM and M30L0R8000T/B0 for the Flash memory. Clock (K). The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KR096A for the PSRAM and M30L0R8000T/B0 for the Flash memory. Wait (WAIT). WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how it behaves, please refer to the M69KR096A datasheet for the PSRAM and to the M30L0R8000T/B0 datasheet for the Flash memory. Flash Chip Enable (EF). The Flash Chip Enable input activates the control logic, input buffers, decoders and sense amplifiers of the Flash memory component. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable pin controls the data outputs during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memories' Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R8000T0/B0 datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 6., Flash Memory DC Characteristics Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 7., Flash Memory DC Characteristics - Voltages). PSRAM Chip Enable input (EP). The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode. PSRAM Write Enable (WP). Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. PSRAM Output Enable (GP). Output Enable, GP, provides a high speed tri-state control, allow- 6/18 M36L0R8060T0, M36L0R8060B0 ing fast read/write cycles to be achieved with the common I/O data bus. PSRAM Upper Byte Enable (UBP). The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. PSRAM Lower Byte Enable (LBP). The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low. PSRAM Configuration Register Enable (CRP). When this signal is driven High, VIH , Write operations load either the value of the Refresh Configuration Register (RCR) or the Bus configuration register (BCR). VDDF Supply Voltage. VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase). VCCP Supply Voltage. VCCP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM operations. VDDQ Supply Voltage. VDDQ provides the power supply for the Flash and PSRAM I/O pins. This allows all Outputs to be powered independently of the Flash and SRAM core power supplies, VDDF and VCCP. VPPF Program Supply Voltage. VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPPF > VPP1 enables these functions (see Tables 6 and 7, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 6., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. 7/18 M36L0R8060T0, M36L0R8060B0 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: EF for the Flash memory and EP for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4. Functional Block Diagram most common example is simultaneous read operations on one of the Flash and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. A22-A23 EF WF RPF WPF GF 256 Mbit Flash Memory WAIT K L A0-A21 VDDF VCCP VPPF VSS DQ0-DQ15 VDDQ EP GP WP CRP UBP LBP AI09314 64 Mbit PSRAM 8/18 M36L0R8060T0, M36L0R8060B0 Table 2. Main Operating Modes Operation Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset PSRAM Read PSRAM Write PSRAM Write Configuration Register PSRAM Standby Any Flash mode is allowed. PSRAM Deep Power-Down Note: 1. 2. 3. 4. EF VIL VIL VIL VIL VIH X GF VIL VIH X VIH X X WF VIH VIL VIH VIH X X LF VIL(2) VIL(2) VIL X X X RPF VIH VIH VIH VIH VIH VIL WAITF(4) EP CRP GP WP LBP,UBP DQ15-DQ0 Flash Data Out PSRAM must be disabled. Flash Data In Flash Data Out or Hi-Z (3) Hi-Z Hi-Z Hi-Z Any PSRAM mode is allowed. Hi-Z Hi-Z VIL The Flash memory must be disabled VIL VIL VIL VIL VIH VIL X VIH VIH VIL VIL VIL VIL X PSRAM data out PSRAM data in PSRAM data in VIH VIH VIL X X X X X X X Hi-Z Hi-Z X = Don't care. LF can be tied to VIH if the valid address has been previously latched. Depends on GF. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R8000T0 datasheet for details. 9/18 M36L0R8060T0, M36L0R8060B0 FLASH MEMORY DEVICES The M36L0R8060T0 and M36L0R8060B0 contain a 256 Mbit Flash memory. For detailed information on how to use the device, refer to the M30L0R8000(T/B)0 datasheet which is available from your local STMicroelectronics distributor. PSRAM DEVICE The M36L0R8060T0 and M36L0R8060B0 contain a 64Mbit PSRAM. For detailed information on how to use the device, see the M69KR096A datasheet which is available from your local STMicroelectronics distributor. 10/18 M36L0R8060T0, M36L0R8060B0 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings Value Symbol TA TBIAS TSTG TLEAD VIO VDDF, VDDQ, VCCP VPPF IO tVPPFH Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Lead Temperature during Soldering Input or Output Voltage Core and Input/Output Supply Voltages Flash Program Voltage Output Short Circuit Current Time for VPPF at VPPFH -0.5 -0.2 -0.2 -25 -25 -65 Max 85 85 125 (1) plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Unit C C C C V V V mA hours 7191395 specification, 2.75 2.45 10 100 100 ECOPACK(R) Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 11/18 M36L0R8060T0, M36L0R8060B0 DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC Measurement Conditions Flash Memory Parameter Min VDDF Supply Voltage VCCP Supply Voltage VDDQ Supply Voltage 1.7 - 1.7 8.5 -0.4 -25 30 16.7 5 0 to VDDQ VDDQ/2 0 to VDDQ VDDQ/2 Max 1.95 - 1.95 9.5 VDDQ +0.4 85 Min - 1.7 1.7 - - -25 30 16.7 Max - 1.95 1.95 - - 85 V V V V V C pF k ns V V PSRAM Unit VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Output Circuit Resistors (R1, R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit VDDQ VDDQ VDDQ/2 0V VDDF VDDQ R1 DEVICE UNDER TEST AI06161 0.1F 0.1F CL R2 CL includes JIG capacitance AI08364B Table 5. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 14 18 Unit pF pF Note: Sampled only, not 100% tested. 12/18 M36L0R8060T0, M36L0R8060B0 Table 6. Flash Memory DC Characteristics - Currents Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=5MHz) IDD1 Test Condition 0V VIN VDDQ 0V VOUT VDDQ EF = VIL, GF = VIH 4 Word Supply Current Synchronous Read (f=54MHz) 8 Word 16 Word Continuous IDD2 IDD3 IDD4 Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) VPPF = VDDF Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (Continuous f=54MHz) in another Bank EF = VDDF 0.2V VPPF = VPPH VPPF = VDDF VPPF = VPPH VPPF = VDDF VPPF VDDF VPPF VDDF 10 23 20 35 mA mA VPPF = VDDF VPPF = VPPH 10 8 20 15 mA mA RPF = VSS 0.2V EF = VDDF 0.2V EF = VIL, GF = VIH VPPF = VPPH 13 16 18 23 25 50 50 50 8 Typ Max 1 1 15 18 20 25 27 110 110 110 15 Unit A A mA mA mA mA mA A A A mA Supply Current IDD6 (1,2) (Dual Operations) 35 47 mA IDD7(1) Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program) 50 2 0.2 2 0.2 0.2 0.2 110 5 5 5 5 5 5 A mA A mA A A A IPP1(1) VPPF Supply Current (Erase) IPP2 IPP3(1) VPPF Supply Current (Read) VPPF Supply Current (Standby) Note: 1. Sampled only, not 100% tested. 2. VDDF Dual Operation current is the sum of read and program or erase currents. 3. The total standby current should be calculates as the sum of the Flash memory standby current plus the PSRAM standby current. 13/18 M36L0R8060T0, M36L0R8060B0 Table 7. Flash Memory DC Characteristics - Voltages Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPPF Program Voltage-Logic VPPF Program Voltage Factory Program or Erase Lockout VDDF Lock Voltage RPF pin Extended High Voltage 1 3.3 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.1 8.5 1.8 9.0 3.3 9.5 0.4 Test Condition Min 0 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V Table 8. PSRAM DC Characteristics Symbol Parameter Test Condition 70ns 85ns 70ns 85ns 104MHz VCCP =VIH or VIL, EP = VIL, IOUT = 0mA 80MHz 66MHz 104MHz 80MHz 66MHz 104MHz ICC3W (1) Min. Typ Max. 25 20 15 12 35 35 30 20 18 15 35 35 30 100 1 1 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A Operating Current: ICC1 (1) Asynchronous Random Read/Write Operating Current: ICC1P (1) Asynchronous Page Read Operating Current: Initial Access, Burst Read/Write ICC2 (1) Operating Current: ICC3R(1) Continuous Burst Read Operating Current: Continuous Burst Write VCC Standby Current Input Leakage Current Output Leakage Current Deep-Power Down Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage IOH = -0.2mA IOL = 0.2mA 80MHz 66MHz ISB (3) VCCP = VDDQ or 0V, EP = VIL 0V VIN VCCP 0V VOUT VCCP VIN = VIH or VIL4 1.4 -0.2 0.8VDDQ 10 ILI ILO 2 IZZ VIH VIL VOH VOL VDDQ + 0.2 0.4 V V V 0.2VDDQ V Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive the output capacitance expected in the actual system. 2. This device assumes a Standby mode if the chip is disabled (EP High). It also automatically goes into Standby mode whenever all input signals are quiescent (not toggling), regardless of the state of E. In order to achieve low standby current, all inputs must be driven to either VDDQ or VSS. 3. ISB(Max) values are measured with RCR2 to RCR0 bits set to `000' (full array refresh) and RCR6 to RCR5 bits set to `11' (temperature compensated refresh threshold at +85C). 4. Operating Temperature is +25C. 14/18 M36L0R8060T0, M36L0R8060B0 PACKAGE MECHANICAL Figure 7. TFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline D D1 e SE E E2 E1 b BALL "A1" ddd FE FE1 A A1 FD SD A2 BGA-Z42 Note: Drawing is not to scale. Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 - - 9.900 0.850 0.350 8.000 5.600 0.100 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 - - 0.3898 0.300 7.900 0.400 8.100 0.200 0.0335 0.0138 0.3150 0.2205 0.0039 0.3976 0.0118 0.3110 0.0157 0.3189 Min Max 1.200 0.0079 Typ Min Max 0.0472 inches 15/18 M36L0R8060T0, M36L0R8060B0 PART NUMBERING Table 10. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VCCP = VDDQ = 1.7 to 1.95V Flash 1 Density 8 = 256 Mbits Flash 2 Density 0 = No Die RAM 1 Density 6 = 64 Mbits RAM 0 Density 0 = No Die Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 0 = 0.13m Flash Technology Multi-Level Design, 85ns speeds; 0.11m PSRAM, 70ns speed, burst mode Package ZAQ = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-free and RoHS Standard packing F = Lead-free and RoHS Tape & Reel packing M36 L 0 R 8 0 6 0 T 0 ZAQ T Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 16/18 M36L0R8060T0, M36L0R8060B0 REVISION HISTORY Table 11. Document Revision History Date 29-Jan-2004 Version 0.1 First Issue TFBGA88 package fully compliant with the ST ECOPACK specification. Document status promoted from Target Specification to Preliminary Data. Flash memory and PSRAM data updated to the version 0.3 of the M30L0R8000x0 and to the version 3.0 of the M69KR096A datasheet. Revision Details 09-Dec-2004 1.0 17/18 M36L0R8060T0, M36L0R8060B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 18/18 |
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